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Addendum
HC908LJ12AD/D Rev. 0, 6/2003 Addendum to MC68HC908LJ12 Technical Data
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This addendum provides information to the following MCU devices: * * MC68HLC908LJ12 (see page 1) MC68HC08LJ12 (see page 9)
The entire MC68HC908LJ12 Technical Data, Rev. 2 (Motorola document number MC68HC908LJ12/D) applies to the these two devices, with exceptions outlined in this addendum. Amendments to MC68HC908LJ12/D, Rev. 2, are documented on page 13.
MC68HLC908LJ12
The MC68HLC908LJ12 is a low-voltage version of the MC68HC908LJ12, with an operating voltage range of 2.4 to 3.3V.
FLASH Memory
The FLASH memory can be read at operating voltages from 2.4 to 3.3V. Program or erase operations require a minimum operating voltage of 2.7V.
Low-Voltage Inhibit (LVI)
The LVI module is not designed for the MC68HLC908LJ12. After an MCU reset, the LVI module is disabled (LVIPWRD = 1 in CONFIG1). The LVIPWRD bit should be left as logic 1 (the default setting).
Electrical Specifications
Electrical specifications for the MC68HLC908LJ12 device are given in the following tables.
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Functional Operating Range Table 1. Operating Range
Characteristic Operating temperature range Operating voltage range Maximum internal operating frequency Symbol TA VDD fOP Value - 40 to +85 2.4 to 2.7 2 2.7 to 3.3 4 Unit
C
V MHz
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Operating voltage for FLASH memory program and erase operations
VDD
2.7 to 3.3
V
DC Electrical Characteristics Table 2. DC Electrical Characteristics (2.4 to 2.7V)
Characteristic(1) Output high voltage (ILOAD = -1.0 mA) All ports Output low voltage (ILOAD = 0.8mA) All ports (ILOAD = 4.0 mA) PTB2-PTB5 (ILOAD = 10.0 mA) PTB0/TxD-PTB1 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 VDD supply current Run(3), fOP = 2 MHz with all modules on with ADC on with ADC off Wait(4), fOP = 2 MHz (all modules off) Stop, fOP = 8 kHz
(5)
Symbol VOH
Min VDD -0.4
Typ(2) --
Max --
Unit V
VOL
--
--
0.4
V
VIH VIL
0.7 x VDD VSS
-- --
VDD 0.3 x VDD
V V
IDD
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- --
5.2 3.8 2.8 2.3 200 27 15 1
mA mA mA mA
25C (with OSC, RTC, LCD(6), LVI on) 25C (with OSC, RTC, LCD(6) on) 25C (with OSC, RTC on) 25C (all modules off) Digital I/O ports Hi-Z leakage current All ports, RST IIL
A A A A A
--
10
2
Addendum to MC68HC908LJ12 Technical Data
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Table 2. DC Electrical Characteristics (2.4 to 2.7V) (Continued)
Characteristic(1) Input current IRQ Capacitance Ports (as input or output) POR re-arm voltage(7) POR rise-time ramp rate(8) Symbol IIN COUT CIN VPOR RPOR VHI RPU1 RPU2 Min -- -- -- 0 0.02 1.5 x VDD -- -- Typ(2) -- -- -- -- -- -- 25 27 Max Unit
1
12 8 100 -- 2 x VDD -- --
A
pF mV V/ms V k k
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Monitor mode entry voltage (at IRQ pin) Pullup resistors(9) PTA0-PTA3, PTD4-PTD7 configured as KBI0-KBI7 RST, IRQ
1. VDD = 2.4 to 2.7 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. 4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC. 6. LCD driver configured for low current mode. 7. Maximum is highest voltage that POR is guaranteed. 8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 9. RPU1 and RPU2 are measured at VDD = 2.6V.
Table 3. DC Electrical Characteristics (2.7 to 3.3V)
Characteristic(1) Output high voltage (ILOAD = -1.0 mA) All ports Output low voltage (ILOAD = 0.8mA) All ports (ILOAD = 4.0 mA) PTB2-PTB5 (ILOAD = 10.0 mA) PTB0/TxD-PTB1 Input high voltage All ports, RST, IRQ, OSC1 Input low voltage All ports, RST, IRQ, OSC1 Symbol VOH Min VDD -0.4 Typ(2) -- Max -- Unit V
VOL
--
--
0.4
V
VIH VIL
0.7 x VDD VSS
-- --
VDD 0.3 x VDD
V V
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Table 3. DC Electrical Characteristics (2.7 to 3.3V) (Continued)
Characteristic(1) VDD supply current Run(3), fOP = 4 MHz with all modules on with ADC on with ADC off Wait(4), fOP = 4 MHz (all modules off) Stop, fOP = 8 kHz
(5)
Symbol
Min
Typ(2)
Max
Unit
IDD
-- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 25 27
8 6 5 3.5 280 38 15 1
mA mA mA mA
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25C (with OSC, RTC, LCD(6), LVI on) 25C (with OSC, RTC, LCD(6) on) 25C (with OSC, RTC on) 25C (all modules off) Digital I/O ports Hi-Z leakage current All ports, RST Input current IRQ Capacitance Ports (as input or output) POR re-arm voltage(7) POR rise-time ramp rate(8) Monitor mode entry voltage (at IRQ pin) Pullup resistors(9) PTA0-PTA3, PTD4-PTD7 configured as KBI0-KBI7 RST, IRQ IIL IIN COUT CIN VPOR RPOR VHI RPU1 RPU2
A A A A A A
pF mV V/ms V k k
-- -- -- -- 0 0.02 1.5 x VDD -- --
10 1
12 8 100 -- 2 x VDD -- --
1. VDD = 2.7 to 3.3 Vdc, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted. 2. Typical values reflect average measurements at midpoint of voltage range, 25 C only. 3. Run (operating) IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects run IDD. 4. Wait IDD measured using external square wave clock source. All inputs 0.2 V from rail. No dc loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait IDD. 5. The 8kHz clock is from a 32kHz clock input at OSC1, for the driving the RTC. 6. LCD driver configured for low current mode. 7. Maximum is highest voltage that POR is guaranteed. 8. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum VDD is reached. 9. RPU1 and RPU2 are measured at VDD = 3V.
4
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HC908LJ12AD/D MC68HLC908LJ12
Oscillator Characteristics Table 4. Oscillator Specifications (2.4 to 2.7V)
Characteristic Internal oscillator clock frequency External reference clock to OSC1(1) Crystal reference frequency(2) Crystal load capacitance(3) Symbol fICLK fOSC fXCLK CL C1 C2 RB RS -- -- -- -- -- Min -- dc Typ See Figure 1. -- 32.768k -- 2 x CL (25p) 2 x CL (25p) 10M 100k Max -- 8M 4.9152M -- -- -- -- -- F F Unit Hz Hz Hz
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Crystal fixed capacitance Crystal tuning capacitance Feedback bias resistor Series resistor(4)
1. No more than 10% duty cycle deviation from 50%. 2. Fundamental mode crystals only. 3. Consult crystal manufacturer's data. 4. Not Required for high frequency crystals.

Table 5. Oscillator Specifications (2.7 to 3.3V)
Characteristic Internal oscillator clock frequency External reference clock to OSC1(1) Crystal reference frequency(2) Crystal load capacitance(3) Crystal fixed capacitance Crystal tuning capacitance Feedback bias resistor Series resistor(4)
1. No more than 10% duty cycle deviation from 50%. 2. Fundamental mode crystals only. 3. Consult crystal manufacturer's data. 4. Not Required for high frequency crystals.
Symbol fICLK fOSC fXCLK CL C1 C2 RB RS
Min -- dc
Typ See Figure 1. -- 32.768k
Max -- 16M 4.9152M -- -- -- -- --
Unit Hz Hz Hz
-- -- -- -- --
-- 2 x CL (25p) 2 x CL (25p) 10M 100k
F F

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70 Internal OSC frequency, fICLK (kHz) 60 50 40 30 20 10 0 2 3 4 Supply Voltage, VDD (V) 5 6 -40C +25C +85C
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Figure 1. Typical Internal Oscillator Frequency ADC Electrical Characteristics Table 6. ADC Electrical Characteristics (2.4 to 3.3V)
Characteristic Supply voltage Input range Resolution Absolute accuracy ADC internal clock Conversion range ADC voltage reference high ADC voltage reference low Conversion time Sample time Monotonically Zero input reading Full-scale reading Input capacitance Input impedance VREFH/VREFL Symbol VDDA VADIN BAD AAD fADIC RAD VREFH VREFL tADC tADS MAD ZADI FADI CADI RADI IVREF 000 3FC -- 20M -- Min 2.4 0 10 Max 3.3 VDDA 10 Unit V V bits VADIN VDDA 1,024 counts Includes quantization. 1 ADC count = 0.5 LSB tADIC = 1/fADIC Notes
See Figure 2 and Figure 3. 32 k VREFL -- VSSA - 0.1 16 5 2M VREFH VDDA + 0.1 -- 17 -- Guaranteed 001 3FF 20 -- 1.6 HEX HEX pF Hz V V V tADIC cycles tADIC cycles
VSSA is tied to VSS internally.
VADIN = VREFL VADIN = VREFH Not tested. Measured at 5V Not tested.
mA
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HC908LJ12AD/D MC68HLC908LJ12
35 30 25
35 30 25
ADC Count Error
ADC Count Error
20 15 10 5 0 -5
20 15 10 5 0 -5
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0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
ADC Input Voltage
(a) VDD = 2.4V at -40C
35 30 25 35 30 25
(d) VDD = 2.7V at -40C
ADC Count Error
ADC Count Error
20 15 10 5 0 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
20 15 10 5 0 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
ADC Input Voltage
ADC Input Voltage
(b) VDD = 2.4V at 25C
35 30 25 35 30 25
(e) VDD = 2.7V at 25C
ADC Count Error
20 15 10 5 0 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
ADC Count Error
20 15 10 5 0 -5 0.0 0.5 1.0 1.5 2.0 2.5 3.0
ADC Input Voltage
ADC Input Voltage
(c) VDD = 2.4V at 85C
(f) VDD = 2.7V at 85C
Note: ADC performance increases with increase in operating voltage and temperature.
Figure 2. Typical ADC Accuracy (2.4V and 2.7V)
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35 30 25
ADC Count Error
20 15 10 5 0 -5
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0.0
0.5
1.0
1.5
2.0
2.5
3.0
ADC Input Voltage
VDD = 3.0 to 3.3V, at -40 to 85C
Figure 3. Typical ADC Accuracy (3V and 3.3V)
Memory Characteristics
At an operating voltage of less than 2.7 V, the FLASH memory can only be read. Program and erase are achieved at an operating voltage of 2.7 to 3.3V. The program and erase parameters in the MC68HC908LJ12 Technical Data are for VDD = 2.7 to 3.3V only. Table 7 shows the ordering numbers for the MC68HLC908LJ12. Table 7. MC68HLC908LJ12 Order Numbers
MC Order Number (1)
MC68HLC98LJ12CFB MC68HLC98LJ12CPB MC68HLC98LJ12CFU
MC68HLC908LJ12 Order Numbers
Package
52-pin LQFP 64-pin LQFP 64-pin QFP
Operating Temperature Range -40 C to +85 C -40 C to +85 C -40 C to +85 C
1. The missing "0" in "908" is intentional.
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HC908LJ12AD/D MC68HC08LJ12
MC68HC08LJ12
The MC68HC08LJ12 is the ROM part equivalent to the MC68HC908LJ12. Table 8. Summary of MC68HC08LJ12 and MC68HC908LJ12 Differences
MC68HC08LJ12 Operating voltages -- 5.0V 10% 12,288 bytes ROM 48 bytes ROM Not used; locations are reserved. Used for testing purposes only. 52-pin LQFP 64-pin LQFP 64-pin QFP MC68HC908LJ12 3.3V 10% 5.0V 10% 12,288 bytes FLASH 48 bytes FLASH FLASH related registers. $FE08 -- FLCR $FF09 -- FLBPR Used for testing and FLASH programming/erasing. 52-pin LQFP 64-pin LQFP 64-pin QFP
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Memory ($C000-$EFFF) User vectors ($FFD0-$FFFF) Registers at $FE08 and $FF09 Monitor ROM ($FC00-$FDFF and $FE10-$FFCF) Available packages
MCU Block Diagram
Figure 4 shows the block diagram of the MC68HC08LJ12.
Memory Map
The MC68HC08LJ128 has 12,288 bytes of user ROM from $C000 to $EFFF, and 48 bytes of user ROM vectors from $FFD0 to $FFFF. On the MC68HC908LJ12 these memory locations are FLASH memory. Figure 5 shows the memory map of the MC68HC08LJ12.
Reserved Registers
The two registers at $FE08 and $FE09 are reserved locations on the MC68HC08LJ12. On the MC68HC908LJ12, these two locations are the FLASH control register and the FLASH block protect register respectively.
Monitor ROM
The monitor program (monitor ROM: $FE10-$FFCF and $FC00-$FDFF) on the MC68HC08LJ12 is for device testing only.
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INTERNAL BUS M68HC08 CPU CPU REGISTERS ARITHMETIC/LOGIC UNIT (ALU) KEYBOARD INTERRUPT MODULE PTA7/ADC3 PTA6/ADC2 PTA5/ADC1 PTA4/ADC0 PTA3/KBI3** PTA2/KBI2** PTA1/KBI1** PTA0/KBI0** PTB7/ADC5 PTB6/ADC4 PTB5/T2CH1 PTB4/T2CH0 PTB3/T1CH1 PTB2/T1CH0 PTB1/RxD PTB0/TxD PTC7/FP26 PTC6/FP25 PTC5/FP24 PTC4/FP23 PTC3/FP22 PTC2/FP21 PTC1/FP20 PTC0/FP19 FP1-FP18 BP0-BP2 COMPUTER OPERATING PROPERLY MODULE POWER-ON RESET MODULE SERIAL PERIPHERAL INTERFACE MODULE PORTD DDRD FP0/BP3 PTD7/KBI7** PTD6/KBI6** PTD5/KBI5** PTD4/KBI4** PTD3/SPSCK PTD2/MOSI PTD1/MISO PTD0/SS
CONTROL AND STATUS REGISTERS -- 96 BYTES USER ROM -- 12,288 BYTES USER RAM -- 512 BYTES
10-BIT ANALOG-TO-DIGITAL CONVERTER MODULE
2-CHANNEL TIMER INTERFACE MODULE 1 PORTB DDRB
PORTA
DDRA
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MONITOR ROM -- 960 BYTES USER ROM VECTOR -- 48 BYTES CLOCK GENERATOR MODULE OSC1 OSC2 CGMXFC 32.768-kHz OSCILLATOR 2-CHANNEL TIMER INTERFACE MODULE 2
#
SERIAL COMMUNICATIONS INTERFACE MODULE (WITH INFRARED ENCODER/DECODER)
PHASE-LOCKED LOOP REAL TIME CLOCK MODULE PORTC DDRC
* RST
SYSTEM INTEGRATION MODULE
* IRQ
EXTERNAL INTERRUPT MODULE
LIQUID CRYSTAL DISPLAY DRIVER MODULE
#
VDDA VDD VSS VREFH VREFL ADC REFERENCE POWER
LOW-VOLTAGE INHIBIT MODULE
* Pin contains integrated pullup device. ** Pin contains integrated pullup device if configured as KBI. High current sink pin, 15mA. High current sink pin, 8mA. # Pins available on 64-pin packages only. Shaded blocks indicate differences to MC68HC908LJ12
Figure 4. MC68HC08LJ12 Block Diagram
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HC908LJ12AD/D MC68HC08LJ12
$0000 $005F $0060 $025F $0260 $BFFF $C000 $EFFF $F000 $FBFF $FC00 $FDFF $FE00 $FE01 $FE02 $FE03 $FE04 $FE05 $FE06 $FE07 $FE08 $FE09 $FE0A $FE0B $FE0C $FE0D $FE0E $FE0F $FE10 $FFCF $FFD0 $FFFF
I/O Registers 96 Bytes RAM 512 Bytes Unimplemented 48,544 Bytes ROM 12,288 Bytes Unimplemented 3,072 Bytes Monitor ROM 1 512 Bytes SIM Break Status Register (SBSR) SIM Reset Status Register (SRSR) Reserved SIM Break Flag Control Register (SBFCR) Interrupt Status Register 1 (INT1) Interrupt Status Register 2 (INT2) Interrupt Status Register 3 (INT3) Reserved Reserved Reserved Reserved Reserved Break Address Register High (BRKH) Break Address Register Low (BRKL) Break Status and Control Register (BRKSCR) LVI Status Register (LVISR) Monitor ROM 2 448 Bytes ROM Vectors 48 Bytes
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Figure 5. MC68HC08LJ12 Memory Map
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Electrical Specifications Functional Operating Range
Electrical specifications for the MC68HC908LJ12 apply to the MC68HC08LJ12 except for the parameters indicated below.
Table 9. Operating Range
Characteristic Operating temperature range Operating voltage range Symbol TA VDD Value - 40 to +85 5.0V 10% Unit
C
V
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RAM Memory Characteristics Table 10. Memory Characteristics
Characteristic RAM data retention voltage Symbol VRDR Min. 1.3 Max. -- Unit V
Notes: Since MC68HC08LJ12 is a ROM device, FLASH memory electrical characteristics do not apply.
MC68HC08LJ12 Order Numbers
These part numbers are generic numbers only. To place an order, ROM code must be submitted to the ROM Processing Center (RPC). Table 11. MC68HC08LJ12 Order Numbers
MC Order Number MC68HC08LJ12CFB MC68HC08LJ12CPB MC68HC08LJ12CFU Package 52-pin LQFP 64-pin LQFP 64-pin QFP Operating Temperature Range -40 C to +85 C -40 C to +85 C -40 C to +85 C
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HC908LJ12AD/D AMENDMENTS TO MC68HC908LJ12/D, REV. 2
AMENDMENTS TO MC68HC908LJ12/D, REV. 2
5.0V DC Electrical Characteristics Pages 394 and 395, Table 23-4 5.0V DC Electrical Characteristics -- Delete LVI typical values and correct note 6.
From:
Characteristic Symbol VTRIPF VTRIPR Min 4.00 4.00 Typ 4.32 4.32 Max 4.70 4.70 Unit V V Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage
Notes: 6. LCD driver configured for high current mode.
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To:
Characteristic Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage
Notes: 6. LCD driver configured for low current mode.
Symbol VTRIPF VTRIPR
Min 4.00 4.00
Typ -- --
Max 4.70 4.70
Unit V V
3.3V DC Electrical Characteristics
Pages 396 and 397, Table 23-5 3.3V DC Electrical Characteristics -- Delete LVI typical values and correct note 6.
From:
Characteristic Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage
Notes: 6. LCD driver configured for high current mode.
Symbol VTRIPF VTRIPR
Min 2.40 2.46
Typ 2.57 2.63
Max 2.88 2.97
Unit V V
To:
Characteristic Low-voltage inhibit, trip falling voltage Low-voltage inhibit, trip rising voltage
Notes: 6. LCD driver configured for low current mode.
Symbol VTRIPF VTRIPR
Min 2.40 2.46
Typ -- --
Max 2.88 2.97
Unit V V
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Oscillator Characteristics
Page 398, Table 23-8 5.0V Oscillator Specifications and Table 23-9 3.3V Oscillator Specifications -- Replace Internal oscillator clock frequency values.
From:
Characteristic Internal oscillator clock frequency Symbol fICLK Min 46k Typ 47k Max 48k Unit Hz
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Characteristic Internal oscillator clock frequency
Symbol fICLK
Min 42.8k
Typ 43.4k
Max 44k
Unit Hz
To:
See Figure 1 . Typical Internal Oscillator Frequency on page 6 of this document.
-- END --
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HC908LJ12AD/D -- END --
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HC908LJ12AD/D Rev. 0 6/2003

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